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24VL024H
4.0
BUS CHARACTERISTICS
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
is not busy.
? During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited, though only the last sixteen will
be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in
first-out fashion.
4.1
Bus Not Busy (A)
4.5
Acknowledge
Both data and clock lines remain high.
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
4.2
Start Data Transfer (B)
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
Note:
The 24VL024H does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
4.3
Stop Data Transfer (C)
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
4.4
Data Valid (D)
slave by not generating an Acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
the slave must leave the data line high to enable the
master to generate the Stop condition (Figure 4-2).
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
SCL
(A)
(B)
(C)
(D)
(C)
(A)
SDA
Start
Condition
FIGURE 4-2:
Address or
Acknowledge
Valid
ACKNOWLEDGE TIMING
Data
Allowed
to Change
Stop
Condition
Acknowledge
Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
SDA
Data from transmitter
Data from transmitter
The transmitter must release the SDA line at this point
allowing the receiver to pull the SDA line low to acknowl-
edge the previous eight bits of data.
? 2008 Microchip Technology Inc.
The receiver must release the SDA line at
this point so the transmitter can continue
sending data.
DS22109A-page 7
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